1. Field of the Invention
The present invention relates to a programming method for recording data in a phase-change memory, and to a reading method for reading data stored in a phase-change memory.
2. Description of the Related Art
Similar to a memory device used in desktop equipment, high performance and high functionality are increasingly demanded of a memory device used for mobile applications, i.e., used for such purposes as portable apparatuses such as portable telephones and various other handheld information devices. A Memory device used for mobile applications must of course have high capacity on the level of, for example, a general-purpose DRAM (Dynamic Random Access Memory), must have a data bit width as large as, for example, 32 bits, must employ access technology such as DDR (Double Data Rate) to enable high-speed access, and moreover, due to its use in mobile devices, must also feature low power consumption. From the standpoint of maintaining long battery life in a portable device in which such a memory device is installed, there is a particularly strong requirement that the memory device continues to hold data despite cut-off of the power supply, i.e., that the memory device is non-volatile. Further, from the standpoint of improving system performance, it is particularly desirable to enable a high-capacity and non-volatile RAM (Random Access Memory) device that is capable of high-speed operation.
As high-speed programmable/readable storage devices, advances have been made in recent years in the development of, for example, MRAM (Magnetic RAM) that uses magnetoresistance effect elements, FeRAM (Ferroelectric RAM) that uses ferroelectric elements, and further, phase-change RAM (PRAM) such as a phase-change memory device that uses phase changes in a substance to store information. Of these, the phase-change memory has received particular attention due to the simplicity of its fabrication, the ease of its application to semiconductor processes, and further, its adaptability to microprocessing and memory element scaling. A method of decreasing the synchronous write bit-width and lowering current consumption of a phase-change memory device has been proposed as a method of reducing programming current in product specifications in Sangbeom Kang et al., “A 0.1 μm 1.8V 256 Mb 66 MHz Synchronous Burst PRAM,” ISSCC Dig. Tech. Papers, pp. 140-141, 644, February, 2006.
A phase-change memory device takes advantage of the properties of chalcogenide materials such as germanium, antimony, and tellurium (Ge, Sb and Te) that, by the application of heat, transition between an amorphous state exhibiting high electrical resistance and a crystalline state exhibiting low electrical resistance. This type of a phase-change memory device is made up from: a memory element having a phase-change element composed of, for example, a chalcogenide; and a selector transistor for selecting one bit. Chalcogenide materials are known to change phase between a crystalline state that is low resistance and an amorphous state that is high resistance due to differences of heat generating processes. This phenomenon was discovered by Stanford Ovshinsky, and chalcogenide materials are now receiving great attention as memory material with the potential for use as a universal memory with names such as OUM (Ovonyx Unified Memory).
Generally, in a phase-change memory, changes between a high-resistance state and low-resistance state in each phase-change element are caused by the joule heat produced by the flow of electric current in the memory element and the time interval of application of the current, and a large current must therefore flow in the memory elements. The high-resistance state, i.e., the amorphous state, is referred to as the “reset state,” and the low-resistance state, i.e., the crystalline state, is referred to as the “set state.” For example, in academic conferences such as the VLSI Symposium and ISSCC (IEEE International Solid-State Circuits Conference), examples have been reported in which the programming current of a phase-change memory, and in particular, the current in the reset programming process for changing the crystalline state to the amorphous state was on the order of 400 μA to 600 μA.
FIG. 1A shows a sectional view of an example of the configuration of a memory cell of a representative phase-change memory device, and FIG. 1B shows an equivalent circuit of the memory cell shown in FIG. 1A.
Memory elements for each bit are formed between semiconductor substrate 800 and upper electrode 801 arranged over semiconductor substrate 800. Each of the memory elements is of a configuration in which phase-change element 803 composed of a phase-change material and heater 805 for heating this phase-change element 803 are connected in a series in a column or post which is perpendicularly formed on a surface of substrate 800. In this case, the phase-change element is composed of a ternary material of Ge—Sb—Tb and is abbreviated as “GST.” Contact material 802 is provided between upper electrode 801 and the upper surface of phase-change element 803 in the figure for electrically connecting the two components. The bottom surface of phase-change element 803 is directly connected to the upper surface of cylindrical heater 805, and the lower surface of heater 805 contacts semiconductor substrate 800. The portion of the surface of semiconductor substrate 800 that contacts heater 805 and the area surrounding this portion are diffusion layer 809D. This diffusion layer functions as the lower electrode for the memory element. In addition, another diffusion layer 809S is formed on the surface of semiconductor substrate 800 separated from the formation position of heater 805, and source electrode 807 is electrically connected to this diffusion layer 809S by way of contact 808. Gate electrode 806 is formed to straddle these two diffusion layers 809D and 809S, and memory cell transistor Tr for selecting this memory cell is formed by gate electrode 806 and diffusion layers 809D and 809S.
In this configuration, upper electrode 801 is typically bit line BL in the memory device as shown in FIG. 1B and serves as the supply source of the voltage and current to the memory cell both when programming and reading this memory element is performed by using a bit line. Phase-change element (GST) 803 and heater 805 are electrically connected in a series between bit line BL (i.e., upper electrode 801) and the drain of memory cell transistor Tr. In the equivalent circuit diagram of FIG. 1B, heater 805 is not clearly shown. The source of memory cell transistor Tr is grounded by way of source electrode 807, i.e., the source is connected to ground potential GND. Gate voltage VG is applied to gate electrode 806 of transistor Tr. The voltage across the source and drain of the transistor Tr is denoted by Vds.
When one bit of data is written to phase-change element 803, i.e., when carrying out programming, voltage is applied across upper electrode 801 and diffusion layer (i.e., lower electrode) 809D to generate heat represented by heat generation amount I2R per unit time based on the value I of electric current that flows in this interval and the resistance R of heater 805. As a result, the heat is conveyed from the interface between heater 805 and phase-change element 803 toward phase-change element 803. At this time, phase-change element 803 can be programmed to either of the amorphous state and crystalline state by changing current I flowing in memory element 803 and the ON time intervals.
FIG. 2 shows a typical current waveform that has been in use for programming of a phase-change memory in the related art. In FIG. 2, the horizontal axis shows the programming time and the vertical axis shows the temperature profile that is made up from the current and resistance. A typical programming method shown in FIG. 2 is explained based on this current waveform.
First, it is assumed that GST (i.e., phase-change element 203), which is the memory material, is in a crystalline state. A temperature surpassing the melting temperature (melting point) Tm of GST is applied to the GST for a short time interval, following which the GST is rapidly cooled for a short time interval. This operation is referred to as “resetting” and is a heat profile for changing the phase of the GST from the crystalline state to the amorphous state. When causing the GST to transition from the amorphous state to the crystalline state, a heat pulse that is longer than at the time of resetting is applied to the GST at temperature Tx that is lower than Tm, followed by slow cooling. This operation is referred to as “setting.” The heat applied to the GST is given by the product of the square of current I flowing through the GST itself or through the resistance element such as the heater material and the resistance R.
When programming is carried out in this way, a hemispherical phase-change portion is produced in phase-change element 803 under the influence of the heat from heater material 805 as shown by reference numeral 804 in FIG. 1A.
FIG. 3 is a graph showing conditions for programming a phase-change element and the definitions and margins for the writing and reading currents. FIG. 3 shows the device characteristics of the phase-change element (GST) when in the amorphous state (i.e., reset state). When voltage VGST applied to the phase-change element is gradually increased while monitoring current that flows to resistance Rreset of the phase-change element when in the reset state, a phenomenon occurs upon reaching a particular fixed voltage Vth in which the slope of the voltage-current curve exhibits a great change and a current that accords with dynamic resistance Rdyn suddenly flows. This phenomenon is called OTS (Ovonic Threshold Switching), voltage Vth being the threshold voltage for bringing about the OTS phenomenon. After the occurrence of OTS, the application of a current of at least Ireset can cause the phase-change element to change to the reset state, or the application of a current of at least Iset(min) but no greater than Isafe can cause the phase-change element to change to the set state. Ireset and Isafe are the upper and lower limits of the margin portion between the reset programming current and set programming current respectively. If the voltage across the two ends of a phase-change element is VGST, VGST where current Isafe is obtained is defined as Vsafe. The voltage at the time of set programming is indicated by Vset. In addition, in FIG. 3, the voltage-current curve for a phase-change element (of resistance Rset) when in the set state is shown by a broken line.
In addition, programming from the crystalline state (set state) to the amorphous state (reset state) can also be carried out by applying a voltage greater than Vsafe to supply the phase-change element with a current of at least Ireset and thus generate a phase-change to the reset state. Voltage at the time of reset programming is shown by Vreset.
Realizing phase-change memory as a commercial product both calls for miniaturization of the device and requires the realization of low-current consumption as performance demanded in recent years for mobile uses. To realize low current consumption, the reduction of the above-described programming current is considered essential. The reset programming current for each bit is currently on the order of 100 μA to 200 μA, and a large-scale reduction of this amount is sought. To achieve a reduction of the programming current, a search is ongoing for materials having compositions suitable for the phase-change element (GST) and investigations are also being conducted to improve the programming method.
Generally, the programming current (or the voltage applied to the phase-change element) and the applied pulse-width are different when causing a transition to the reset state (i.e., high-resistance state) and when causing transition to the set state (i.e., low-resistance state) in the programming of a phase-change memory. Typically, the reset pulse width is on the order of 100 ns, and the set pulse width is on the order of 500 ns. In a high-speed phase-change memory, the reset pulse width is expected to be 10 ns or less, and the set pulse width is expected to be on the order of 30 ns.
Despite reduction of the reset programming current with advances in the development of a phase-change memory, currently, in the programming of a phase-change memory, programming pulses having two different widths for setting and resetting must be used, and a current supply required for each of these pulses must be implemented. In other words, circuits are required both for generating and controlling each pulse and for controlling and supplying each current.
When realizing a non-volatile RAM, however, the operating speed must be on the same order as that of a typical universal DRAM. If a synchronous DRAM is considered as the universal DRAM, the programming speed demanded for an operating speed of 100 MHz is 10 ns or less for each address. Thus, even if it is supposed that a resetting speed of 10 ns or less and a setting speed of 30 ns or less could be realized in a phase-change memory, set programming cannot be effected in pulse signals of one shot, and the above-described operating speed cannot be achieved. To suppress the programming time interval, a configuration is possible in which limits are placed on programming and reading. For example, programming may be carried out only in continuous determined page units, but adopting such a configuration not only prevents the high-speed and random access as in an ordinary RAM, but also leads to an increase in the scale of the control circuits in the memory array portion in a memory device. Increase in the scale of the control circuits in the memory array portion has a significant effect on chip size in a semiconductor memory device having a phase-change memory, and has a particularly important influence on reading speed, thereby affecting high-speed reading.
Japanese Patent Laid-Open publication No. 2002-203392 (JP-A-2002-203392), which corresponds to EP-A-1 202 285, discloses a phase-change memory that, by stacking a plurality of phase-change material layers having different crystallization characteristics, is capable of storing multiple values per cell, i.e., can store the information of a plurality of bits. In addition, an example of a phase-change memory is also described in Yi-Chou Chen et al., “A new thin-film cross-point non-volatile memory using threshold switching properties of phase-change chalcogenide,” 2004/IEEE, pp. 685-690.
As described hereinabove, a phase-change memory is sought that not only reduces power consumption but also shortens the time interval for set programming. However, such a phase-change memory suffers from the drawbacks that, in programming the phase-change memory, the generation of pulses of different time widths during set programming and during reset programming hinders the high-speed operation of the phase-change memory, and further, complicates the circuits for generating these pulses. In addition, an increase in the speed of reading information from the phase-change memory while maintaining low power consumption is also sought.